In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from "CPU Identification")...

CPU-World, CPUID for Intel Xeon 3.40 GHz – Nocona stepping D CPUID without CMPXCHG16B CPU-World, CPUID for Intel Xeon 3.60 GHz – Nocona stepping E CPUID with...

shrink of Intel's Core microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE41[Bit 19] flag. SSE4.2 added STTNI (String and Text New Instructions)...

as CPUID family 6 model 22. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model...

the Family 0Fh processors. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0F(h) (where the h...

revision and RAM clock rate. It also provides information on the system's GPU. CPUID HWMonitor Benchmark (computing) GPU-Z Speccy "CPU-Z 2.15". 17 March 2025...

P-cores and E-cores on early versions of Alder Lake CPUs reported different CPUID models. This has caused issues with digital rights management systems that...

documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core." The 0.25 μm Tonga core was...

must be determined by using CPUID to query the maximum physical-address width supported by the processor by invoking CPUID with function 80000008H and...

otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model...

to access current and future "model-specific registers", as well as the CPUID instruction to determine which features are present on a particular model...

copying, logical operations, program control, and special instructions (e.g., CPUID). In addition to the opcode, many instructions specify the data (known as...

Physical Address Extension (PAE) but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions)...

instruction set consists of several separate sets each having their own unique CPUID feature bit. However, they are typically grouped by the processor generation...

queried by the CPUID command. As noted in the Pentium II Processor update documentation from Intel, "although this processor has a CPUID of 163xh, it uses...

by setting the motherboard clock multiplier to 2. Package number: 26050 CPUID: Family 5, Model 8, Stepping 0 L1-Cache: 32 + 32 KiB (Data + Instructions)...

a smaller L2 cache. Merom-L has only one processor core and a different CPUID model. The desktop version of Merom is Conroe and the dual-socket server...

processor is earlier than the 486. Starting with the Intel Pentium, the CPUID instruction reports the processor model. However, the above method remains...

"Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket...

only publicly documented by Intel with the release of the Pentium Pro. The CPUID instruction can be used to identify the availability of PSE on x86 CPUs...

instruction rdseed are available with Intel Broadwell CPUs and AMD Zen CPUs. The CPUID instruction can be used on both AMD and Intel CPUs to check whether the...

information Marketed by Intel Designed by Intel Common manufacturers Intel TSMC CPUID code unknown Product code unknown Performance Max. CPU clock rate P-cores:...

Photo of CPUID for Transmeta Crusoe TM5800 800 MHz on Fujitsu P2040...

enabled by the BMI bit in CPUID. Intel officially considers LZCNT as part of BMI, but advertises LZCNT support using the ABM CPUID feature flag. BMI1 is available...

are supported modes when the processor is not in long mode. A bit in the CPUID extended attributes field informs programs in real or protected modes if...

four cores report the same CPUID model 0206A7h and are closely related. The stepping number cannot be seen from the CPUID but only from the PCI configuration...

have a smaller L2 cache. Conroe-L has only one processor core and a new CPUID model. The mobile version of Conroe is Merom, the dual-socket server version...

processor microarchitecture. This is a separate extension using its own CPUID flag and is described on its own page and not below. Intel Haswell processors...

about their features, including stepping level. For example, executing CPUID instruction with the EAX register set to '1' on x86 CPUs will result in...

the chip identified itself as an 80486 and disabled the CPUID instruction by default. CPUID support could be enabled by first enabling extended CCR registers...