In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from "CPU Identification")...
237 KB (13,489 words) - 16:18, 24 June 2025
CPU-World, CPUID for Intel Xeon 3.40 GHz – Nocona stepping D CPUID without CMPXCHG16B CPU-World, CPUID for Intel Xeon 3.60 GHz – Nocona stepping E CPUID with...
264 KB (14,984 words) - 21:36, 16 July 2025
shrink of Intel's Core microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE41[Bit 19] flag. SSE4.2 added STTNI (String and Text New Instructions)...
23 KB (1,583 words) - 12:40, 4 July 2025
the Family 0Fh processors. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0F(h) (where the h...
11 KB (1,142 words) - 01:48, 18 November 2024
Alder Lake (section CPUID incoherence)
P-cores and E-cores on early versions of Alder Lake CPUs reported different CPUID models. This has caused issues with digital rights management systems that...
58 KB (2,781 words) - 15:28, 13 July 2025
as CPUID family 6 model 22. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model...
57 KB (3,500 words) - 01:59, 17 May 2025
revision and RAM clock rate. It also provides information on the system's GPU. CPUID HWMonitor Benchmark (computing) GPU-Z Speccy "CPU-Z 2.15". 17 March 2025...
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micro-operation cache hit or miss Supervisor Mode Execution Prevention CPUID Faulting support The built-in GPU has 6 or 16 execution units (EUs), compared...
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information Marketed by Intel Designed by Intel Common manufacturers Intel TSMC CPUID code unknown Product code unknown Architecture and classification Application...
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documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core." The 0.25 μm Tonga core was...
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Physical Address Extension (PAE) but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions)...
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instruction set consists of several separate sets each having their own unique CPUID feature bit. However, they are typically grouped by the processor generation...
85 KB (4,667 words) - 21:58, 16 July 2025
otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model...
116 KB (7,807 words) - 03:16, 22 July 2025
processor microarchitecture. This is a separate extension using its own CPUID flag and is described on its own page and not below. Intel Haswell processors...
51 KB (4,089 words) - 23:38, 15 May 2025
"Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket...
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by setting the motherboard clock multiplier to 2. Package number: 26050 CPUID: Family 5, Model 8, Stepping 0 L1-Cache: 32 + 32 KiB (Data + Instructions)...
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Retrieved 3 November 2011. "x86, x64 Instruction Latency, Memory Latency and CPUID dumps". 22 October 2011. Retrieved 3 November 2011. Shvets, Gennadiy (8...
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only publicly documented by Intel with the release of the Pentium Pro. The CPUID instruction can be used to identify the availability of PSE on x86 CPUs...
4 KB (584 words) - 13:21, 26 December 2023
instruction rdseed are available with Intel Broadwell CPUs and AMD Zen CPUs. The CPUID instruction can be used on both AMD and Intel CPUs to check whether the...
26 KB (2,638 words) - 21:55, 9 July 2025
four cores report the same CPUID model 0206A7h and are closely related. The stepping number cannot be seen from the CPUID but only from the PCI configuration...
61 KB (2,688 words) - 19:44, 9 June 2025
queried by the CPUID command. As noted in the Pentium II Processor update documentation from Intel, "although this processor has a CPUID of 163xh, it uses...
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processor is earlier than the 486. Starting with the Intel Pentium, the CPUID instruction reports the processor model. However, the above method remains...
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copying, logical operations, program control, and special instructions (e.g., CPUID). In addition to the opcode, many instructions specify the data (known as...
17 KB (1,169 words) - 22:24, 15 July 2025
groups of instructions. x86 calling conventions x86 instruction listings CPUID 680x0, a competing architecture in the 16-bit and early 32-bit eras PowerPC...
105 KB (10,898 words) - 22:59, 15 July 2025
2024; 9 months ago (2024-10-10) Designed by AMD Common manufacturer TSMC CPUID code Family 1Ah Cache L1 cache 80 KB (per core): 32 KB instructions 48 KB data...
35 KB (3,421 words) - 22:41, 21 July 2025
have a smaller L2 cache. Conroe-L has only one processor core and a new CPUID model. The mobile version of Conroe is Merom, the dual-socket server version...
17 KB (1,787 words) - 14:42, 20 February 2025
original U2xxx series "Merom-L" used a special version of the Merom chip with CPUID number 10661 (model 22, stepping A1) that only had a single core and was...
276 KB (9,952 words) - 01:50, 21 July 2025
microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23, replacing Kentsfield, the previous model. Like its predecessor...
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Photo of CPUID for Transmeta Crusoe TM5800 800 MHz on Fujitsu P2040...
16 KB (1,669 words) - 19:08, 21 June 2025
high-end server and supercomputer microprocessor. Steppings: C0, C1 and C2. CPUID: 0007000604h (stepping C0), 0007000704h (stepping C1) or 0007000804h (stepping...
27 KB (1,456 words) - 20:26, 15 April 2024