Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in...
6 KB (489 words) - 04:18, 26 April 2023
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM Sempron and Athlon models exclude...
186 KB (10,618 words) - 05:39, 24 May 2024
SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16–F16C, XOP, FMA4. All models support single socket configurations...
89 KB (2,189 words) - 20:37, 15 April 2024
MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM AMD in its technical documentation...
28 KB (1,744 words) - 10:15, 4 March 2024
SSE1 - 2 - 3 - 3s - 4.1 - 4.2 - 4a, NX bit, AMD64, AMD-V, IOMMU, AES, CLMUL, AVX, XOP, FMA4, F16C, ABM, Turbo Core 2.0, PowerNow!, ECC Codenamed: Vishera...
19 KB (973 words) - 20:48, 18 May 2024
Bridge) available at its introduction (including SSSE3, SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD; ABM, XOP, FMA4...
36 KB (3,750 words) - 09:25, 13 June 2024
applications" in the CAESAR Competition. Advanced Vector Extensions (AVX) CLMUL instruction set FMA instruction set (FMA3, FMA4) RDRAND The instruction...
25 KB (2,185 words) - 19:42, 13 June 2024
AES-NI), out of which six implement the AES algorithm, and PCLMULQDQ (see CLMUL instruction set) implements carry-less multiplication for use in cryptography...
20 KB (501 words) - 19:26, 18 May 2024
instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT)...
23 KB (1,049 words) - 21:32, 29 May 2024
Architecture Instructions set x86 Instructions x86-64 Extensions AES-NI CLMUL RDRAND SHA TXT MMX SSE SSE2 SSE3 SSSE3 SSE4 SSE4.1 SSE4.2 AVX AVX2 AVX-512...
22 KB (1,937 words) - 07:47, 11 June 2024
CLMUL, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AVX, F16C, CLMUL...
28 KB (861 words) - 05:21, 2 March 2023
X86 instruction listings (section CLMUL instructions)
many/most x86 CPUs, while others are specific to a narrow range of CPUs. CLMUL RDRAND Advanced Vector Extensions 2 AVX-512 x86 Bit manipulation instruction...
337 KB (15,653 words) - 01:56, 13 June 2024
(previously known as 10ESF) Instruction set x86, x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX...
18 KB (1,440 words) - 10:36, 27 March 2024
Instruction set AMD64/x86-64, MMX(+), SSE1, 2, 3, 3s, 4.1, 4.2, 4a, AES, CLMUL, AVX, XOP, FMA3, FMA4, CVT16/F16C, BMI1, ABM, TBM, AMD-V Physical specifications...
13 KB (1,270 words) - 02:37, 25 February 2024
which does the multiplication of polynomials over the Galois field GF(2) (clmul, clmulh, clmulr). These are useful for cryptography and CRC checks of data...
130 KB (13,557 words) - 07:43, 9 June 2024
Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 AES-NI, RDRAND, CLMUL, SHA VT-x, VT-d Physical specifications Cores 4–24 Products, models, variants...
16 KB (548 words) - 01:02, 12 June 2024
cryptography PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional...
24 KB (2,586 words) - 15:01, 3 May 2024
cryptography PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional...
8 KB (677 words) - 11:41, 15 December 2023
programming portal Advanced Vector Extensions (AVX) AES instruction set CLMUL instruction set F16C FMA instruction set Intel ADX XOP instruction set Intel...
18 KB (1,403 words) - 08:13, 15 January 2024
SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, AES-NI, CLMUL, RDRAND Extensions SGX, SHA, TXT, VT-x, VT-d Physical specifications Cores...
114 KB (7,681 words) - 22:33, 1 June 2024
E-cores) Instruction set x86-64 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3...
65 KB (4,904 words) - 12:19, 16 June 2024
Intel 10 nm FinFET process Instruction set x86, x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, SGX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4...
14 KB (1,057 words) - 12:54, 3 June 2024
Lake Instruction set x86-64 Instructions x86-64 Extensions MMX, AES-NI, CLMUL, FMA3, RDRAND SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 AVX, AVX2, TXT...
51 KB (1,828 words) - 10:10, 20 April 2024
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, CVT16, F16C, Turbo Core Memory support:...
89 KB (3,396 words) - 21:59, 8 May 2024
SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, VT-x, VT-d Physical specifications Cores 8-64 Package...
12 KB (323 words) - 20:49, 3 June 2024
Instruction set x86-64 Instructions x86-64, Intel 64 Extensions MMX, AES-NI, CLMUL, RDRAND, FMA3, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2,...
13 KB (943 words) - 10:44, 16 June 2024
AVX-512 (with Zen 4 and later), FMA3, CVT16/F16C, ABM, BMI1, BMI2, AES, CLMUL, RDRAND, SHA, SME, AMD-V, AMD-Vi Physical specifications Cores up to 128...
32 KB (3,484 words) - 07:43, 16 June 2024
Instructions sets: x87, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, CLMUL, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2, SHA. All Ryzen-branded CPUs...
84 KB (7,508 words) - 13:47, 16 June 2024
Skylake Instruction set x86-64 Instructions x86-64 Extensions MMX, AES-NI, CLMUL, FMA3, RDRAND SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 AVX, AVX2, TXT...
51 KB (2,551 words) - 15:58, 6 June 2024
SSE, MCA, ACPI, SSE2, NX bit, SMT, SSE3, SSSE3, SSE4, SSE4.2, AES-NI, CLMUL, RDRAND, SHA, MPX, SME, SGX, XOP, F16C, ADX, BMI, FMA, AVX, AVX2, AVX-VNNI...
104 KB (10,709 words) - 12:45, 16 June 2024