Back end of line

Back end of the line or back end of line (BEOL) is a process in semiconductor device fabrication that consists of depositing metal interconnect layers onto a wafer already patterned with devices. It is the second part of IC fabrication, after front end of line (FEOL). In BEOL, the individual devices (transistors, capacitors, resistors, etc.) are connected to each other according to how the metal wiring is deposited.

The individual devices are connected by alternately stacking oxide layers (for insulation purposes) and metal layers (for the interconnect tracks). The vias between layers and the interconnects on the individual layers are thus formed using a structuring process.^[1]

Common metals are copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. For modern IC processes, more than 10 metal layers can be added in the BEOL.

Before 1998, practically all chips used aluminium for the metal interconnection layers, whereas copper is mostly used nowadays.^[2]

Steps of the BEOL are:^[1][3]

1. Silicidation of source and drain regions and the polysilicon region.
2. Adding a dielectric (first, lower layer is pre-metal dielectric (PMD) – to isolate metal from silicon and polysilicon), CMP processing it
3. Make holes in PMD, make a contacts in them.
4. Add metal layer 1
5. Add a second dielectric, called the inter-metal dielectric (IMD)
6. Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVD process.

   Repeat steps 4–6 to get all metal layers.

7. Add final passivation layer to protect the microchip

After BEOL there is a "back-end process" (also called post-fab), which is done not in the cleanroom, often by a different company. It includes wafer test, wafer backgrinding, die separation, die tests, IC packaging and final test.

Quality control in back‑end of line (BEOL) is essential for ensuring reliable packaging and interconnection performance. Non‑contact three‑dimensional (3D) optical metrology techniques, such as coherence scanning interferometry (CSI), confocal microscopy, and focus variation, are employed to assess critical parameters without damaging delicate structures. These techniques support measurements of:

• Bump height, coplanarity, and uniformity in flip‑chip and ball grid array (BGA) packaging
• Thickness and uniformity of adhesive or underfill layers used in die attachment
• Warpage, flatness, and surface integrity of encapsulated packages
• Surface roughness and topographic changes induced by thermal cycles or handling

A case study demonstrated the use of CSI through a temperature-controlled chamber (20 °C to 380 °C) to non‑invasively monitor silicon wafer topography during Rapid Thermal Processing (RTP). Optical aberrations caused by windowed thermal environments were corrected using a Linnik interferometer setup, enabling sub‑nanometre precision in surface roughness and shape evolution over repeated heating steps.^[4]

• Front end of line (FEOL)
• Integrated circuit
• Phosphosilicate glass

• "Chapter 11: Back End Technology". Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Prentice Hall. 2000. pp. 681–786. ISBN 0-13-085037-3.
• "Chapter 7.2.2: CMOS Process Integration: Backend-of-the-line Integration". CMOS: Circuit Design, Layout, and Simulation. Wiley-IEEE. 2010. pp. 199–208 [177–79]. ISBN 978-0-470-88132-3.
• "Chapter 2: Technology Know-How: From Silicon to Devices". Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer, doi:10.1007/978-3-030-39284-0ISBN 978-3-030-39284-0, 2020. p. 82 (2.9.4 BEOL: Connecting Devices)